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Archive for the ‘Vlsi’ Category


Sreenivasa Kothmasu has this interesting website on Analog Vlsi and other general things including job search, interview questions, etc

Analog and Other Stuff – Analog and Other Stuff.

Access Meebo

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CMOS Types of Power Concerns


Types of Power Concerns
• Dynamic power
– Mainly due to charging/discharging
parasitic capacitance – dictated by
switching activity
– Types of concerns:
– Optimal battery life
– System cost: sustained peak power
dictates packages and cooling needs
– System feasibility: short-term peak
power effects on integrity/reliability
• Leakage power
– Optimal battery life in standby mode
– At 90nm, significant component of total
power
• Power integrity
– Ensure power supply infrastructure
operates correctly and reliably in the
target system

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Power Modeling and Optimization for NoCs

Analysis of power consumption on switch fabrics in network routers
Ye, T.T.; Benini, L.; De Micheli, G.;
Design Automation Conference, 2002. Proceedings. 39th , 10-14 June 2002
Pages:524 – 529

A power and performance model for network-on-chip architectures
Banerjee, N.; Vellanki, P.; Chatha, K.S.;
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings , Volume: 2 , 16-20 Feb. 2004
Pages:1250 – 1255 Vol.2

Managing power consumption in networks on chips
Simunic, T.; Boyd, S.P.; Glynn, P.;
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 12 , Issue: 1 , Jan. 2004
Pages:96 – 107

System level power modeling and simulation of high-end industrial network-on-chip
Bona, A.; Zaccaria, V.; Zafalon, R.;
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings , Volume: 3 , 16-20 Feb. 2004
Pages:318 – 323 Vol.3

Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
Jingcao Hu; Marculescu, R.;
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings , Volume: 1 , 16-20 Feb. 2004
Pages:234 – 239 Vol.1

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Tutorial on Cadence SoC encounter

Lab 1 Synthesis with Cadence BuildGates and Place and Route with SOC Encounter
Cadence Worldwide University Software Programs .

Cadence Digital Implementation Flow

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